Time we had some new chip technology.

And good to see IBM backroom boys still on the job.

Inavate Magazine

IBM ‘block of flats’ chip design could put 100 billion tr...

IBM has unveiled a new chip design which could allow 100 billion transistors on a silicon chip as small as a human fingernail.IBM’s new chip technology is

I am still unclear as to how much smaller these chips are. .7 nanometers vs 2 nanometers would make things almost 3 times smaller, an improvement to be sure, but am I missing something? Because most announcements like this are orders of magnitude smaller. IMO the bigger + of these chips is their efficiency improvement.

1 hour ago, npts2020 said:

I am still unclear as to how much smaller these chips are. .7 nanometers vs 2 nanometers would make things almost 3 times smaller, an improvement to be sure, but am I missing something? Because most announcements like this are orders of magnitude smaller. IMO the bigger + of these chips is their efficiency improvement.

+1 for being prepared to say "I don't understand" or words to that effect.

Chips today are 2 dimensional so are measured by area, not length.

So reducing linear dimensions by a factor of 10 reduces the area by a factor of 100 and so on.
Quite a significant reduction in its day.

but IBM are proposing 3 dimensional chips, making an even more dramatic saving. So 1/3* 1/3 * 1/3 =1/27.

Obviously not as goo as 1/1000 would be, but not to be sniffed at even so.

2 hours ago, npts2020 said:

I am still unclear as to how much smaller these chips are. .7 nanometers vs 2 nanometers would make things almost 3 times smaller, an improvement to be sure, but am I missing something? Because most announcements like this are orders of magnitude smaller. IMO the bigger + of these chips is their efficiency improvement.

0.7 nm vs 2.1 nm would mean 1/3 the size in each dimension, which means 9x as many transistors per unit area. Most announcements I recall (when I was paying closer attention to AMD vs Intel) are similar kinds of jumps. They went from 90 nm — 65 nm — 45 nm — 32 nm — 24/28 nm — 22 nm — 20 nm — 16 nm — 14 nm — 10 nm — 7 nm — 5 nm

https://en.wikipedia.org/wiki/List_of_semiconductor_scale_examples

Roughly doubling the number of transistors seems to be the point where it’s been economical to switch scales. Chip manufacturers aren’t going to wait and get left behind while a competitor comes out with a significantly faster processor

(edit/rant: I tried just giving the numbers with no units and the board software kept parsing groups of them as phone numbers)

 

Anyway, I thought that stacked layers were already in existence, but for passive devices. Actively powered ones have a heat dissipation issue, which is mentioned in passing, but it’s not really explained how that’s been solved, other than that these were more efficient.

Processors are already putting up to 300 Billion transistors on a single die ( NVidia Rubin GPU ).
The biggest issue at these scales is electron migration ( e^- going places you don't want them to go ) through mechanisms like tunneling, and the only current solution is massive redundancy, and error correction, making a lot of those transistors un-useable for the actual task.

I think the next big change to keep Moore's Law going, has to be a materials change and/or power consumption reduction to enable massively vertical transistor manufacturing

as a bonus, if you watch this video, Anastasi has to be the hottest chip design engineer, with a sexy accent that I can't quite place.