Enthalpy Posted October 9, 2017 Share Posted October 9, 2017 Hello you all! Here's a means to produce a sine wave voltage, very pure, with metrologic amplitude, whose frequency can be varied over 2+ octaves in the audio range - this combination may serve from time to time. It uses sums of square waves with accurate shape and timeshift. A perfectly symmetric square wave has no even harmonics. Adding two squares shifted by T/6 suppresses all 3N hamonics as the delay puts them in opposition; this makes the waveform well-known for power electronics. Two of these waveforms can be added with T/10 shift to suppress all 5N harmonics, then two of the latter with T/14 shift, and so on. A filter removes the higher harmonics as needed. The operation makes sense, and may be preferred over direct digital synthesis, because components and proper circuits may provide superior performance. Counters produce accurate timings. If a fast output flip-flop outputs a zero 1ns earlier or later than a one, at 20kHz it leaves -90dBc of second harmonic and at 1kHz -116dBc, but at 1MHz less interesting -56dBc. If the propagation times of the output flip-flops match to 0.5ns, at 20kHz they leave -100dBc of third, fifth, seventh... harmonic and at 1kHz -126dBc. 74AC Cmos output buffers have usually less than 15ohm and 25ohm impedance at N and P side. On a 100kohm load, the output voltage equals the power supply to +0 -200ppm. 5ohm impedance mismatch contributes -102dBc to the third harmonic, less at higher ones. Common resistor networks achieve practically identical temperatures and guarantee 100ppm matching, but measures give rather 20ppm. This contributes -110dBc to the third harmonic, less at higher ones. This diagram example would fit 74AC circuits. Programmable logic, Asic... reduce the package count and may use an adapted diagram. To suppress here the harmonics multiple of 2, 3, 5 and 7, it uses 8 Cmos outputs and resistors. As 3 divides 9, the first unsqueezed harmonic is the 11th. A counter by 210 has complementary outputs so that sending the proper subsets to 8-input gates lets RS flip-flops change their state at adequate moment. Programmable logic may prefer GT, LE comparators and no RS. I would not run parallel counters by 6, 5 and 7 instead of 210 as these would inject harmonics. The RS flip-flops need strong and fast outputs. Adding an octuple D flip-flop is reasonable, more so with programmable logic. I feel paramount that the output flip-flops have their own regulated and filtered power supplies, for instance +-2.5V, and the other logic circuits separated supplies like +-2.5V not touching the analog ground. That's a reason to add an octuple D flip-flop to a programmable logic chip. For metrologic amplitude, the output supplies must be adjusted. All the output flip-flops must share the same power supplies, unless the voltages are identical to 50ppm of course. A fixed filter can remove the higher harmonics if the fundamental varies by less than 11 minus margin, and a tracking filter for wider tuning is easy as its cutoff frequency is uncritical. The filter must begin with passive components due to the slew rate, and must use reasonably linear components. ---------- I tried almost three decades ago the circuit squeezing up to the fifth harmonic, and it works as expected. Squeezing up to the third is even simpler, with a Johnson counter by 6 and two resistors. Measuring the spectrum isn't trivial, for instance Fft spectrometers can't do it; most analog spectrometers need help by a linear high-pass filter that attenuates the fundamental. Marc Schaefer, aka Enthalpy 1 Link to comment Share on other sites More sharing options...
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