abateNth Posted March 31, 2008 Share Posted March 31, 2008 Anyone familiar with CPU error codes, production pools thereof, knows of the command instruction set. And, the execution bit that is parametrically an execute flag. Now, what if, say, grounding circuits were introduced, board length*width. Hang with me here, it's nothing more than a dissipater coil. Here's what you do, calculate, at factory, voltage, calibrate. Induce algorithmic type encryption. Yes, serialize. Introduce as many errors as you feel, now, through known technology, introduce this grounding circuit. Which, if broken, triggers an embedded chip. Which, of course through error code or such as user required intervention signals. That's my idea at randomization. Software technique analysis shows effectiveness. Link to comment Share on other sites More sharing options...
John Cuthber Posted April 1, 2008 Share Posted April 1, 2008 "That's my idea at randomization" Indeed. Link to comment Share on other sites More sharing options...
bascule Posted April 2, 2008 Share Posted April 2, 2008 Anyone familiar with CPU error codes, production pools thereof, knows of the command instruction set. Instruction Set Architecture? [gibberish] HINT: Random amalgamations of words do not necessarily form meaningful expressions in the English language Link to comment Share on other sites More sharing options...
abateNth Posted April 2, 2008 Author Share Posted April 2, 2008 Pentium D 915, no RISC involved. Error control-bit, ON, Board Level. Register on that... Link to comment Share on other sites More sharing options...
John Cuthber Posted April 2, 2008 Share Posted April 2, 2008 Does abateNth pass the Turing test? Link to comment Share on other sites More sharing options...
abateNth Posted April 3, 2008 Author Share Posted April 3, 2008 The Turing machine, analog system. Used primarily for number systems within the Real Plane. Suitable for restraining rounding error in constants. Known, as well as unknown. Mainly derivational. Worked with large sources, and was the reverse of a dummy-terminal. Fed input, until solution was found for known desired. BTW, most operators not having keys to use, as typewriters were not electronic at the time; use the slide-rule. Given rate on a very busy day, it handled around 200 solves per user. Get busy, Link to comment Share on other sites More sharing options...
iNow Posted April 3, 2008 Share Posted April 3, 2008 I think that's a no. Link to comment Share on other sites More sharing options...
bascule Posted April 3, 2008 Share Posted April 3, 2008 Pentium D 915, no RISC involved The Pentium 4 architecture on which the Pentium D is based operates by decoding the CISC operations of x86 into RISC micro-ops. While it executes a CISC ISA, the core architecture is fundamentally RISC. That said, you don't appear to speak English, so I'm afraid this explanation is falling on deaf ears. Link to comment Share on other sites More sharing options...
abateNth Posted April 4, 2008 Author Share Posted April 4, 2008 Quit terminal operations, idiot. I Ain't had now Industry Standard Architecture since my last 286. Went to Enhanced ISA, why didn't you. as far as the tapped at registers, within CPU code, I'm aware of DMA access. Which, current set up, is explicitly denied; as there's no buffer space. I don't have a get away with it CD Writer, aka: External. Dry space... Link to comment Share on other sites More sharing options...
iNow Posted April 4, 2008 Share Posted April 4, 2008 Quit terminal operations, idiot. This is helpful... How, exactly? Link to comment Share on other sites More sharing options...
Pangloss Posted April 4, 2008 Share Posted April 4, 2008 Well, it was helpful in giving me something to do with my mod hat on. Link to comment Share on other sites More sharing options...
Recommended Posts