A few RISC pipeline/branch questions

What's the difference between "delay" and "penalty?" For example: branch delay, branch penalty, load delay, load penalty.

Never-mind about above. In the questions, "delay" was meant to pertain to a single instruction, and by "penalty" the question meant the total penalty, given various statistics about the program (percentage of branches, etc). Damn ambiguous questions

In regards to the classic 5-stage pipeline (IF ID EX MEM WB): If there is no forwarding, the correct target address of a branch will not be "available" (to other instructions) until the after WB stage, right? So, whenever there is a branch, the instruction at the target can't be fetched until the cycle after the branches WB stage? I.e. this will have to happen, (correct?):

1   2   3   4   5   6   7 <- cycles.
IF  ID  EX  MEM WB  <- branch instruction.
stalls----  IF  ID  EX  MEM WB  <- instruction at branch target.

I think this is correct because the program counters are just registers, and registers aren't updated until the WB stage.

Edited August 14, 201213 yr by wordtourmother