Book says 16 bits is equivalent to 32,678 bytes

[DylsexicChciken]

Book says 16 bits is equivalent to 32,678 bytes. How did my book get that?

 

 

The 16-bit address means a load word instruction can load any word within
a region of plus or minus 2^15 or 32,768 bytes (213 or 8192 words) of the address in the base
register rs.

 

Edited February 23, 2015 by DylsexicChciken

[Sensei]

They are talking about relative offset from address.

-32768.... +32767 bytes

In total 65536 bytes, where 0 is in middle.

 

Read more about signed short (integer).

Edited February 23, 2015 by Sensei

[Strange]

How did my book get that?

 

Plus or minus 2¹⁵.

[John Cuthber]

Has anyone ruled out the idea that the author simply made a mistake?

[Strange]

Has anyone ruled out the idea that the author simply made a mistake?

 

I can't see anything wrong with it. (But I have bad cold, so I may be missing something.)

[timo]

In case this more basic point was the issue: The book does not say 16 bit were equal to several thousands of bytes (they are equal to two bytes, of course). What it says is that if memory locations are encoded with 16 bit then there are 2^16 different possible memory locations that can be encoded: 2^15 in each direction with one left for the nitpickers or those who count zero as having a direction.

[John Cuthber]

A 16 bit address bus lets you access 65536 different locations.

 

In that sense (and, without the book's context, it's hard to comment on what sense is being used) 16 bits is equivalent to 65536 bytes.

It's still 65536 however you choose to label them.

I still suspect an error rather than anything complicated.

[Strange]

The quoted text is obviously referring to the use of a 16 bit registe to define an offset from a base register (hence the "plus or minus 2^15 or 32,768 bytes").

 

We don't know what book this is. Off the top of my head, I don't know what processor has a base address register called RS (MIPS, maybe?).

[DylsexicChciken]

I think my book made a mistake, my teacher had the same book and the same edition with different wording which was clearer and meant something different from the exact version I have, which is weird.

 

32,768 bytes is way too large to be equivalent to 16 bits. 32,768 bytes is 32,768 * 8 bits = 262,144 bits. There are only 2 bytes in 16 bits because there are only 8 bits in 1 byte. The book probably meant plus or minus 32,768 integers, not bytes.

Edited February 25, 2015 by DylsexicChciken

[Strange]

32,768 bytes is way too large to be equivalent to 16 bits.

 

Not if it uses byte addressing.

 

The book probably meant plus or minus 32,768 integers, not bytes.

 

It says plus or minus 8192 words (integers0, which implies it does use byte addressing. Is this MIPS or something else?

[Sensei]

I think my book made a mistake, my teacher had the same book and the same edition with different wording which was clearer and meant something different from the exact version I have, which is weird.

 

32,768 bytes is way too large to be equivalent to 16 bits. 32,768 bytes is 32,768 * 8 bits = 262,144 bits. There are only 2 bytes in 16 bits because there are only 8 bits in 1 byte. The book probably meant plus or minus 32,768 integers, not bytes.

 

You have all this wrong in your head.

Integers are even bigger than bytes. On 32 bit machine "int" has 4 bytes..

 

This book is CORRECT.

Except little fact of saying +-32768, while in reality it's -32768.... +32767 bytes (and this part about 213, not sure what does it means. Maybe this CPU has function like Motorola MOVEM.L for loading/writing all CPU registers at once. It has 38-40 registers?).

 

They didn't say that buffer with size 32768 bytes is copied. Just word at offset from base register is accessed.

 

Imagine:

 

char buffer[ 65536 ];

char *ptr = buffer + 32768;

 

now on

ptr[ 0 ] refers to middle of buffer

ptr[ -32768 ] refers to the beginning of buffer

and

ptr[ +32767 ] refers to the end of buffer

 

ptr is like base register in book.

and in brackets you have 16 bit signed integer offset.

 

If you compile such code, there will be generated:

 

Do you see our 16 bit integer offsets.. ?

eax is loaded by data from stack.

Then it's used as base register, and byte from memory location at hard coded offset 0x8000 (-32768) copied.

 

Edited February 25, 2015 by Sensei

[John Cuthber]

I suspect that " (213 or 8192 words) " should be

(2^13 or 8192 words)

and a superscript got lost there somehow.

[Sensei]

I suspect that " (213 or 8192 words) " should be

(2^13 or 8192 words)

and a superscript got lost there somehow.

 

I agree.

The most probable answer, is the most probably the right one.

[Strange]

I suspect that " (213 or 8192 words) " should be

(2^13 or 8192 words)

and a superscript got lost there somehow.

 

That confused me for a while, but I think you are right.

[Enthalpy]

Is there any machine where address offsets are understood as signed? I know none up to now. And since the Ram size often differs from the maximum addressable space, it matters.

[DylsexicChciken]

The 16-bit address means a load word instruction can load any word within

a region of plus or minus 2^15 or 32,768 bytes (plus or minus 2^13 or 8192 words) of the address in the base

register rs. Similarly, add immediate is limited to constants no larger than plus or minus 2^15.

We see that more than 32 registers would be difficult in this format, as the rs and rt

fields would each need another bit, making it harder to fit everything in one word.

 

 

I copied the paragraph from the book and forgot to edit some mistakes. The quote above is the fixed version. Yes this is referring to MIPS instruction code. I don't know how to do the plus or minus sign, so I put it in English instead of the plus or minus symbol.

 

It's basically saying you can store 32,768 bytes in the space of 2^16 bits in the address section of I-format instruction. I am still having trouble wrapping my head around this

Edited February 26, 2015 by DylsexicChciken

[Sensei]

It's basically saying you can store 32,768 bytes in the space of 2^16 bits in the address section of I-format instruction. I am still having trouble wrapping my head around this.

 

Are we only using the positive 2^15, instead of the entire 2^16, to store unsigned addresses? Even then, bytes is too large. The former would make sense if the book said 32,768 bits instead of bytes.

See link

http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html

There is showed where index-offset is going inside of instruction, in which bits it is stored.

They are showed by chain of "i" (especially lw instruction).

 

It's signed 16 bit integer.

 

Local variables on stack of currently executed function are always stored at negative offset from base register.

Well, it's even clearly visible on screen-shot that I gave in post #11.

EBP-0x10014 = EBP - 65556

(but it's Intel)

Edited February 26, 2015 by Sensei

[Thorham]

It's basically saying you can store 32,768 bytes in the space of 2^16 bits in the address section of I-format instruction.

No, it's not saying that, it's saying that with a 16 bit value you can address 65536 bytes.

 

Here's an example:

 

You have a pointer A, and the signed 16 bit value they're talking about in the book. We'll call that B. What you can do now, is use an addressing mode that adds A and B together, and uses the end result as a new pointer.

 

Say A = 100000, and B = 30000. The resulting pointer would be 130000. If B would be -30000, then the resulting pointer would be 70000.

 

The signed 16 bit range is -2^15 to 2^15-1.

 

Example in Motorola 68000 assembly language:

 

    lea     100000,a0      ; set the pointer to 100000
    move.w  #30000,d0       ; set the signed value to 30000
    move.b  #123,(a0,d0.w)  ; add ponter and signed value together
                            ; to form a new pointer, which points to
                            ; 130000, and write the value
                            ; 123 to that location

Edited February 26, 2015 by Thorham

[DylsexicChciken]

No, it's not saying that, it's saying that with a 16 bit value you can address 65536 bytes.

 

Here's an example:

 

You have a pointer A, and the signed 16 bit value they're talking about in the book. We'll call that B. What you can do now, is use an addressing mode that adds A and B together, and uses the end result as a new pointer.

 

Say A = 100000, and B = 30000. The resulting pointer would be 130000. If B would be -30000, then the resulting pointer would be 70000.

 

The signed 16 bit range is -2^15 to 2^15-1.

Example in Motorola 68000 assembly language:

 

 

So the 2^16 bits can store 65536 addresses, each address containing 1 byte. But how does the plus or minus 2^15 and 32,768 bytes factor into this? Plus or minus 2^15 implies there are negative addresses, meanwhile 32,768 bytes is only half the amount of addresses that can be represented.

[pzkpfw]

Imagine a bit of machine code that needs to jump to a different address.

 

The equivalent of "if x = y then go to subroutine five".

 

If the address offset jumped to could only be positive, you'd have a program that could only go forward. You'd never be able to do loops and such. (Unless you used all absolute addresses and "hard coded" the destination of jumps backwards).

 

The Z80, for example had a relative jump that allowed an 8 bit (1 byte) address offset. That amounted to a jump of 128 bytes forwards or 127 backwards; not just 256 bytes forwards. (Note that the Z80 had a 16 bit address bus, so 8 bit offsets did not cover the full address range, from any given location).

 

 

So the 2^16 bits can store 65536 addresses, each address containing 1 byte. But how does the plus or minus 2^15 and 32,768 bytes factor into this? Plus or minus 2^15 implies there are negative addresses, meanwhile 32,768 bytes is only half the amount of addresses that can be represented.

 

Sorry, but you tend to be very sloppy with terminology. (Not that I'm claiming infallibility).

 

It's not 2^16 bits, it's 16 bits. (In this example). That doesn't "store" 65536 addresses, a 16 bit value can hold a number (assuming simple unsigned integer, e.g. not BCD or something) from 0 to 2^16 - 1, or 0 to 65535. That might be used to point to an address, i.e. 65536 different locations. What's at those locations might or might not be a byte - it depends on the CPU architecture. For relative or offset addressing, we need to be able to look forwards or backwards from a given location, so as a signed value, those 16 bits allows a range approximately + or - 32767. Essentially (approx) half of the 65536 forwards, half of it backwards.

Edited February 26, 2015 by pzkpfw

[Strange]

Is there any machine where address offsets are understood as signed? I know none up to now. And since the Ram size often differs from the maximum addressable space, it matters.

 

It doesn't make any difference whether you consider the offsets as signed or unsigned - because you are doing modulo arithmetic. For example, the offset might be #0xffffffff - now you could interpret this as "-1" and thefore subtract 1 from the base addres. On the other hand, you could cosider this as the largest possible positive value: but when this is added to the base address it "wraps round" and ends up addressing the memory address one before the base address - exactly the same as if you had subtracted 1.

It's basically saying you can store 32,768 bytes in the space of 2^16 bits in the address section of I-format instruction.

 

No: you can address +/- 32768 bytes using 16 bits. In other words, the 16 bit register can "point to" any location which is 32768 bytes above or below the base address.

[pzkpfw]

(

It doesn't make any difference whether you consider the offsets as signed or unsigned - because you are doing modulo arithmetic. For example, the offset might be #0xffffffff - now you could interpret this as "-1" and thefore subtract 1 from the base addres. On the other hand, you could cosider this as the largest possible positive value: but when this is added to the base address it "wraps round" and ends up addressing the memory address one before the base address - exactly the same as if you had subtracted 1.

 

Assuming an addressing mode where the offset has the same magnitude as the the base address. Not always the case.

 

)

Edited February 27, 2015 by pzkpfw

[Strange]

(

 

Assuming an addressing mode where the offset has the same magnitude as the the base address. Not always the case.

 

)

 

Maybe. Although, the offset is likely to be scaled to match the addressing of the base register. (And the original quote implies byte addressing for both).

 

And as the OP is already confused by the simple case ...

[Sensei]

Assuming an addressing mode where the offset has the same magnitude as the the base address. Not always the case.

 

This is almost never the case, because ideally we want to have offset inside of instruction, not in additional parameter. To reduce needed memory accesses.

 

From link that I gave post #17:

 

 

Encoding bits inside of instruction long word is our offset/index.

 

Motorola 680x0 has 8 bits offset -128..+127

and 16 bits offset -32768...+32767

 

MIPS OP is working on has 16 bits offset -32768...+32767

 

Simply the most significant bit of offset is extended to the all higher bits of real addressing bus.

0x8000 (=%1000 0000) is becoming 0xFFFF8000, and

0x7FFF (=%0111 1111) is becoming 0x00007FFF,

[Thorham]

So the 2^16 bits can store 65536 addresses, each address containing 1 byte.

In this case, the 16 bit number is added to a pointer to form a new pointer. The 16 bit number itself is not an address. Think of it as an index.

 

But how does the plus or minus 2^15 and 32,768 bytes factor into this?

The 16 bit value isn't really an addres, but a number that's added to an address to form a new address.

 

Plus or minus 2^15 implies there are negative addresses, meanwhile 32,768 bytes is only half the amount of addresses that can be represented.

Not exactly. Addresses are always positive values. The values that get added to addresses don't have to be positive. If you have address 100000, then it's no problem to subtract 32000 from it.

 

What's at those locations might or might not be a byte - it depends on the CPU architecture.

Most CPUs out there use 8bit bytes.

Edited February 27, 2015 by Thorham