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D Flip Flop Circuit


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Hi gang,


I have a Master-slave D flip-flop with Clear and Preset in front of me. I'm a little confused on the output (which is Q and ~Q). If I understand this correctly, when the clock is coming down, negative edge, the input D matters and Q changes.


Assuming Q starts at 0, If the clk is 0 and D is 1, that means Q is always 0 unless clk changes to 1... then Q changes to 1 ONLY if clk changes to 0 again and D remains 1? Then following this example D changes to 0, unless clk goes into a negative edge it wont change Q?


My next question is the clear and preset, do these override clk and D? From what I read a positive edge flip flop will change the output Q instantly with no regard for the clock. Finally, preset and preset_n are just not opposites yes? My book refers to preset but labels the input Preset_n?


I wish my book showed me a example of a timing diagram of this circuit in action.

Edited by Silvanoshei
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This might make the Master-Slave relationship a bit more clear. There are two flip flops, with the second only changing in response to a change in the first.


If DMaster = 1 and Clock = 1, QMaster = 1

DSlave = QMaster

If DSlave = 1 and Clock = 0, QSlave = 1


There are also truth tables out there which I generally find to be helpful to look at.


Just to clarify typically preset/clear are referenced as set and reset.



My next question is the clear and preset, do these override clk and D?


Essentially yes.



There are free online circuit simulators out there. Logic.ly/demo is good for basic stuff and you can probably find others with a bit of searching.

Edited by Endy0816
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