# Computer Organisation D-Flip flop register timing diagram

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Hi guys,

I have come across a problem on a sample exam paper and I don't understand how to draw the timing diagram. I know how to draw timing diagrams but not ones with data as shown here and with two lines criss-crossing at many locations as shown in the picture. I don't understand how that is 'translated' through the clock signal. Any help is appreciated

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So the ideas to show that there is a bus, such as set of data or address signals, that change. Some may go up and some down (or not change at all). The short hand is to show the overall change by two diagonal lines, just so it is clearer where the change is happening. I have also seen these drawn without the sloping lines, so you just get a series of rectangles with the values in.

So, in this case, what happens is that the data is "captured" (and held) on the rising edge of the clock. So look at the value at each rising edge and draw the data changing (the sloping lines) at that point, with the value at that clock edge written inside. That would so much easier if I drew a picture... I'll try a post one in a minute...

Does that help?

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6 hours ago, Strange said:

So the ideas to show that there is a bus, such as set of data or address signals, that change. Some may go up and some down (or not change at all). The short hand is to show the overall change by two diagonal lines, just so it is clearer where the change is happening. I have also seen these drawn without the sloping lines, so you just get a series of rectangles with the values in.

So, in this case, what happens is that the data is "captured" (and held) on the rising edge of the clock. So look at the value at each rising edge and draw the data changing (the sloping lines) at that point, with the value at that clock edge written inside. That would so much easier if I drew a picture... I'll try a post one in a minute...

Does that help?

That helps some bit thanks, so all I have to do is shift the 0xA register over until the start of it meets a rising edge of the clock? Does the one before 0x9 become 0x0 so if the data is being shifted to the right?

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That helps some bit thanks, so all I have to do is shift the 0xA register over until the start of it meets a rising edge of the clock?

Yes. But I hope you understand why you are doing that

Are you happy with a timing diagram for a D-type with just one data signal? This is just the same but using the sloping lines and hex values as a "shorthand" for drawing all the individual data lines

And yes, yes

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